Optimizing Parity Bits for Error Detection and Correction for Memories Using Matrix based Technique

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Addepalli Bhanu Prathyusha, Parasa Sivadurgarao


Complementary Metal Oxide Semiconductor knowledge has been residential for source to Multiple Cell Upsets (MCUs). Data storing in memory for different uses, MCUs has been demanding to the radiation particles. Error Correction Code having low complexity, decoding and encoding which is one of the more frequently technique for protecting the memories. By storing the nearby bits in memory MCUs had been trouble. The procedure would correct and detect nearby bits as many as achieved which had producing technique. In order to solve the problem of higher number of parity bits in Matrix based code, a technique is proposed in this paper. Equality bits have been concentrated with using power & stoppage. The proposed technique for these parameters have efficient and producing one to protect the memory. This procedure had been useful for applications of speed and parity bits having surely restricted.

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